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chipsalliance / UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Apache License 2.0
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bindAny should not look in the current instance for HighConn, only parent instance. #1074

Open pieter3d opened 4 months ago

pieter3d commented 4 months ago

See https://github.com/chipsalliance/Surelog/issues/3958#issuecomment-1931459568

In ElaboratorListener.cpp when bindAny is called and it comes from a port HighConn in VpiListener.cpp, searching for the net by name should not start at the top of the stack. Doing so will cause the HighConn to incorrectly reference the port net inside the module, if the net connected to the port (the desired high conn) has the same name as the port itself.

Assuming I'm not missing something here, this seems like a real bug and makes me wonder how this was never seen before.

alaindargelas commented 4 months ago

The instStack_ has to be popped temporarily while binding high_conn so is skips the current module scope.