Open alaindargelas opened 5 days ago
@mysoreanoop, The work involved for your particular problem is a subset of the work that would be needed for https://github.com/chipsalliance/UHDM/issues/1037.
First please extend the UHDM data model with the 5 boxes object model described here: https://github.com/chipsalliance/UHDM/issues/1037
To avoid confusion with Vpi objects (Module) prefix the netlist object model with nl:
nlModule, nlInstance, nlPort, nlNet, nlInstPort Create the full schema with the relations described in the link. In the existing UHDM::design object, add a list of nlModule (call it topNetlists), similar to the existing topModules.
The nlInstance object needs to have an additional pointer to a vpiStmt (always block, cont assign) since we are creating here a netlist at RTL level instead of the DNI model being a gate level model.
Make a PR with just the model definition for now. I'll describe how to populate it once we have the model checked in.
You backtracing algorithm will traverse the topNetlists->nlModule instead of traversing the vpi API as you described.
@mysoreanoop wrote in: https://github.com/chipsalliance/Surelog/issues/3975
I'm trying to backtrack output ports from the topModule this way: 1a. Parse all continuous and procedural assignments. 1b. For each assignment, populate an lhs2rhs map (vpiFullName is used as unique ID).
Is there a more efficient way to do this without having to parse all assignments and submodule IOs? Specifically, given a vpiHandle to an output port, could I get all the sources of that port/net and keep doing that recursively? Would procedural assignments with if-else branches complicate things?