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chipsalliance / UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Apache License 2.0
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Upgrade cap'n'proto to head #986

Closed hs-apotell closed 1 year ago

hs-apotell commented 1 year ago

Upgrade cap'n'proto to head

hs-apotell commented 1 year ago

@alaindargelas I have done this upgrade before also #878 and something in your workflow keep pulling this back #905. Please check your workflow actions to ensure this update doesn't get reverted.

hzeller commented 1 year ago

What is happening here in the windows compile ?

hs-apotell commented 1 year ago

Looks like Windows MSVC target isn't verified on capnp repository's CI and that's failing. It's an issue with variadic arguments for macros.

hzeller commented 1 year ago

Maybe you need to do git submodule update --init --recursive for your version of UHDM being updated @alaindargelas ?