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chipsalliance / VeeR-ISS

Apache License 2.0
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Floating Point Register #19

Closed HamzaShabbir517 closed 2 years ago

HamzaShabbir517 commented 2 years ago

Hello i have enable the single precision floating point to perform some test but it seem that the register file is according to double precision that is 64 bits. Is their any parameter to make the floating point register file length to 32 when we are using single precision only

And i also want to know about the vector extension as i try to run vector instruction but it gave me an illegal instruction error. and there is also no parameter to read vector register file

jrahmeh commented 2 years ago

Hi Hamza,

The code uses 64-bit wide registers and nan-boxing for storing single precision values into 64-bit-wide registers. If the F extension is enabled and D extension is disabled, then the tracing/logging code will print the least significant 32-bits of the internal registers. Please give this a try: enable F and disable D. You do this by using "--isa imaf".

Joe

HamzaShabbir517 commented 2 years ago

is the vector extension is supported into whisper