search

chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
269 stars 61 forks source link

Compilation error #1

Closed tunghoang290780 closed 4 years ago

tunghoang290780 commented 4 years ago

Hello

I compile SweRVolf in Ubuntu 16.04, Verilator 4.010 and get a compilation error. I guess this is due to using an incompatible Verilator version

/usr/local/verilator/4.010/bin/verilator -f swervolf_0.vc --trace -Wno-fatal %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.2/design/lib/beh_lib.sv:149: syntax error, unexpected begin %Error: Exiting due to 1 error(s) %Error: Command Failed /usr/local/verilator/4.010/bin/verilator_bin -f swervolf_0.vc --trace -Wno-fatal Makefile:16: recipe for target 'Vswervolf_core_tb.mk' failed

I just modify code as below then compilation went well. image

However, beh_lib.sv is automatically generated by toolchain (fusesoc) so it should be fixed in upstream repo.

/T

olofk commented 4 years ago

Hi Tung,

I just tried with verilator 4.010 and get the same error. It works fine with Verilator 4.006 so I will file a bug report against verilator to see if it's a bug there

olofk commented 4 years ago

I fixed this in SweRV now. Please update and see if the problem disappears

tunghoang290780 commented 4 years ago

Thank olofk,

I closed this issue