chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
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Replace deprecated AXI infrastructure #10

Closed olofk closed 4 years ago

olofk commented 4 years ago

The AXI components from @pulp-platform that are currently used in SweRVolf have been deprecated. For all these components, there exists replacement components that shall be used instead. This issue tracks the replacement of the four identified components that need to be replaced

  1. axi2apb used in axi_uart_wrapper shall be replaced by an axi->axi_lite bridge followed by an axi_lite->apb bridge
  2. Replace axi_slice_dc used between cpu and memory in the nexys a7 target with an axi_cdc
  3. Replace axi_mem_if used in axi_multicon with.... not sure really
  4. Replace axi_node with axi_xbar. Rewrite axi_intercon_gen for the new component

Best case we can do these things one at a time. Worst case there is some backwards compatibility breaks that forces us to do it all at once

Does this look right @zarubaf @accuminium @fabianschuiki ? Any comments on this?

fabianschuiki commented 4 years ago

This looks right! I think @accuminium is working on the axi_mem_if replacement. The switch to axi_cdc is also strongly recommended, as it does not expose the brittle internals of the domain crossing to the outside, and is much easier to constrain properly. There are RTL attributes on the signals that need to be constrained, so if your EDA tool preserves them, that makes adding the necessary set_max_delay easier.

olofk commented 4 years ago

Thanks @fabianschuiki . That's good to know. Does this imply that the current axi_mem_if still works with newer versions of the axi repo? That would be good, since it would allow me to use the current one until the new one is ready.

Good reminder about the CDC too. I remember now having some questions about how that was handled in the old component. Maybe I'll start with that one then

olofk commented 4 years ago

Work started in the axi branch Successfully replace the AXI CDC now

andreaskurth commented 4 years ago

This look right! I think @accuminium is working on the axi_mem_if replacement.

Indeed a new SRAM controller with an AXI slave port is under development and will be upstreamed to the axi repository soon.

Does this imply that the current axi_mem_if still works with newer versions of the axi repo? That would be good, since it would allow me to use the current one until the new one is ready.

axi2mem in the axi_mem_if repository should do the job in the meantime. It has not been updated in a while, but it should still be compatible with the current infrastructure in axi.

olofk commented 4 years ago

AXI interconnect seems to work too. Waiting for upstream response to know if I should put the interconnect generator in a fork or use the upstream repo

olofk commented 4 years ago

This is all done now and axi_intercon_gen is upstreamed. I ended up dropping the dependencies on axi2mem and axi2apb