chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
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Updated OpenOCD .cfg files for proper ICACHE flush #13

Closed JanMatCodasip closed 3 years ago

JanMatCodasip commented 4 years ago

@olofk - Hi Olof,

I noticed that in SweRVolf 0.7, ICACHE is enabled by default. Actually, to make the ICACHE work with OpenOCD, two more things need to be done:

1) A very recent OpenOCD version has to be used that has support for "step-start" event.

2) OpenOCD needs to be configured to flush the SweRV's Icache.

Feel free to reach back if anything.

Regards, Jan

olofk commented 3 years ago

Thanks @JanMatCodasip! I had completely missed this one. Pulling it in now.

JanMatCodasip commented 3 years ago

I had completely missed this one. Pulling it in now.

Thank you, no problem.

Once SweRV 1.8 is adopted, I expect one more change to the OpenOCD configuration files. Namely: riscv set_mem_access abstract so that OpenOCD can access all memory, including the core-local ones.

olofk commented 3 years ago

Aha. Good to know. Can you please add that as a patch as well? I'm just about to release a new SweRVolf with 1.8, so it would be great to add this change as well before the release

JanMatCodasip commented 3 years ago

Can you please add that as a patch as well? I'm just about to release a new SweRVolf with 1.8

@olofk - Of course. Here you are: https://github.com/chipsalliance/Cores-SweRVolf/pull/23