Closed profroyk closed 4 years ago
Success (sort of) - I was able to successfully simulate w/ verilator after I built a new version of verilator from the github repository. This was using MobaXterm running a bash terminal session w/ WSL/Ubuntu 18.04.
I was not able to get run successfully w/ either target=sim --tool= modelsim or target=nexys_a7 when running from Windows 10 even though I installed fusesoc. Here is that error sequence (pardon the dos control characters):
[1;37mINFO: Generating ::swervolf-swerv_default_config:0.7 [1;31mERROR: Setup failed : "python3 C:\Users\rkravitz.cache\fusesoc\chipsalliance.org_cores_SweRV_EH1_1.6\configs/swerv_config_gen.py C:\Users\rkravitz.cache\fusesoc\generated\swervolf-swerv_default_config_0.7\swerv_default_config_input.yml" exited with an error code. See stderr for details.
I was able to get further when I tried on WSL/Ubuntu 18.04. Got stymied/stuck because I couldn't get the latest version of verilator. I did sudo apt-get update followed by a sudo apt-get install verilator but apt-get said I had the latest version (3.916). Other than building from source I'm not sure how to get a later version. So, if it won't be possible to get fusesoc working on ubuntu 20.04, a pointer in the direction of how to get a later version of Verilator would be appreciated.
I am hoping that a fix to make this work w/ ubuntu 20.04 is possible.
Thanks Roy
Hi Roy,
Sorry for not getting to this until now and even now I'm not really sure what to make of this. The error messages don't make any sense to me. Are you still trying to get this going? If so, have there been any changes lately?
Hi Olof
Thanks for the response. To be truthful, I don't remember when I sent that report. It may have been prior to starting on RVfpga where I worked directly w/ fuseSoc as a precursor to starting on RVfpga. Since then I have been focused on RVfpga which uses SweRVOlf but does not require fuseSoC so I haven't gotten back to it.
Roy
On Thu, Sep 24, 2020 at 7:46 AM Olof Kindgren notifications@github.com wrote:
Hi Roy,
Sorry for not getting to this until now and even now I'm not really sure what to make of this. The error messages don't make any sense to me. Are you still trying to get this going? If so, have there been any changes lately?
— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/chipsalliance/Cores-SweRVolf/issues/15#issuecomment-698391819, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAZF7J4TBM4KPDEXELXWAELSHNLSVANCNFSM4ODU2OKA .
--
Roy Kravitz Westside Program Director Electrical and Computer Engineering Department Maseeh College of Engineering and Computer Science Portland State University
503-913-1678 (M) roy.kravitz@pdx.edu ece.pdx.edu
Hi Roy,
Thanks for the background. I'm taking the liberty to close this one, as it's not likely anyone will continue the investigation. Anyone with similar issues is free to reopen or file a new bug
I just started working w/ fusesoc and swervolf and got this error when following the steps in the README.md file. I cloned the repositories today so should have the latest.
I am running ubuntu 20.04 LTS and python 3.8 which I have aliased to python. I've looked through the .core files but I couldn't find what intcon was being generated from. I have Verilator 4.028 2020-02-06 rev v4.026-92-g890cecc1 installed but I don't think I'm getting that far.
Thanks Roy Kravitz (roy.kravitz@pdx.edu)
Here's the console log:
profroyk@roy-ASUSLaptop:~$ cd $WORKSPACE profroyk@roy-ASUSLaptop:~/fpga/swervolf$ fusesoc run --target=sim swervolf WARNING: Unknown item version in section Root INFO: Preparing ::cdc_utils:0.1 INFO: Preparing chipsalliance.org:cores:SweRV_EH1:1.6 INFO: Preparing fusesoc:utils:generators:0.1.5 INFO: Preparing ::jtag_vpi:0-r5 INFO: Preparing pulp-platform.org::common_cells:1.16.4 INFO: Preparing ::simple_spi:1.6.1 INFO: Preparing ::uart16550:1.5.5-r1 INFO: Preparing ::verilog-arbiter:0-r3 INFO: Preparing ::wb_common:1.0.3 INFO: Preparing pulp-platform.org::axi:0.23.0-r1 INFO: Preparing ::wb_intercon:1.2.2-r1 INFO: Preparing ::swervolf:0.7 INFO: Generating ::swervolf-intercon:0.7 Traceback (most recent call last): File "/usr/local/bin/fusesoc", line 8, in
sys.exit(main())
File "/usr/local/lib/python3.8/dist-packages/fusesoc/main.py", line 836, in main
args.func(cm, args)
File "/usr/local/lib/python3.8/dist-packages/fusesoc/main.py", line 359, in run
run_backend(
File "/usr/local/lib/python3.8/dist-packages/fusesoc/main.py", line 429, in run_backend
edalizer.run()
File "/usr/local/lib/python3.8/dist-packages/fusesoc/edalizer.py", line 88, in run
self.run_generators()
File "/usr/local/lib/python3.8/dist-packages/fusesoc/edalizer.py", line 139, in run_generators
for gen_core in _ttptttg.generate(self.cache_root):
File "/usr/local/lib/python3.8/dist-packages/fusesoc/edalizer.py", line 411, in generate
Launcher(args[0], args[1:], cwd=generator_cwd).run()
File "/usr/local/lib/python3.8/dist-packages/fusesoc/utils.py", line 35, in run
subprocess.check_call(map(str, [self.cmd] + self.args), cwd=self.cwd,),
File "/usr/lib/python3.8/subprocess.py", line 359, in check_call
retcode = call(*popenargs, *kwargs)
File "/usr/lib/python3.8/subprocess.py", line 340, in call
with Popen(popenargs, **kwargs) as p:
File "/usr/lib/python3.8/subprocess.py", line 854, in init
self._execute_child(args, executable, preexec_fn, close_fds,
File "/usr/lib/python3.8/subprocess.py", line 1702, in _execute_child
raise child_exception_type(errno_num, err_msg, err_filename)
NotADirectoryError: [Errno 20] Not a directory: 'python'
profroyk@roy-ASUSLaptop:~/fpga/swervolf$
profroyk@roy-ASUSLaptop:~/fpga/swervolf$ alias