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chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
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SImulation run error #17

Closed altuSemi closed 4 years ago

altuSemi commented 4 years ago

Hi,

Thanks for sharing this repository. I use Ubuntu 18.04, python 3.6m. After installing fusesoc, I try to run the simulation and an include file is not found although it exists:

INFO: Generating ::swervolf-swerv_default_config:0.7 Traceback (most recent call last): File "/home/altus/.cache/fusesoc/chipsalliance.org_cores_SweRV_EH1_1.6/configs/swerv_config_gen.py", line 55, in g.run() File "/home/altus/.cache/fusesoc/chipsalliance.org_cores_SweRV_EH1_1.6/configs/swerv_config_gen.py", line 50, in run shutil.copy2(os.path.join(cwd, f),f) File "/usr/lib/python3.6/shutil.py", line 263, in copy2 copyfile(src, dst, follow_symlinks=follow_symlinks) File "/usr/lib/python3.6/shutil.py", line 120, in copyfile with open(src, 'rb') as fsrc: FileNotFoundError: [Errno 2] No such file or directory: '/tmp/tmpy6_4a230/core/configs/snapshots/default/common_defines.vh' ERROR: Setup failed : "python3 /home/altus/.cache/fusesoc/chipsalliance.org_cores_SweRV_EH1_1.6/configs/swerv_config_gen.py /home/altus/.cache/fusesoc/generated/swervolf-swerv_default_config_0.7/swerv_default_config_input.yml" exited with an error code. See stderr for details.

ls /tmp/tmpy6_4a230/core/snapshots/default/ common_defines.vh pic_ctrl_verilator_unroll.sv defines.h pic_map_auto.h pd_defines.vh whisper.json perl_configs.pl

Thanks Udi

altuSemi commented 4 years ago

Ok, solved with admin rights

NFO: Running INFO: Running simulation Loading RAM contents from hello.vh Releasing reset SweRV+FuseSoC rocks

Finito