chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
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verilator + openocd + gdb simulation issue #25

Open kidonglee opened 3 years ago

kidonglee commented 3 years ago

I have some problem when running simulation with "verilator+openocd+gdb". 'step' or 'continue' command in gdb do not work well. (there is no next gdb prompt after the commands) I don't know what the problem is. Please help me.

Actually, I run the test as below,

Thank you.