search

chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
269 stars 61 forks source link

error during run simulation #3

Closed zhanjf closed 4 years ago

zhanjf commented 4 years ago

hi, when I execute the command fusesoc run --target=sim swervolf

the following error met,

INFO: Generating ::swervolf-swerv_default_config:0 Traceback (most recent call last): File "/home/work/.cache/fusesoc/chipsalliance.org_cores_SweRV_EH1_1.4/configs/swerv_config_gen.py", line 2, in from fusesoc.capi2.generator import Generator ImportError: No module named fusesoc.capi2.generator ERROR: Setup failed : "python /home/work/.cache/fusesoc/chipsalliance.org_cores_SweRV_EH1_1.4/configs/swerv_config_gen.py /home/work/.cache/fusesoc/generated/swervolf-swerv_default_config_0/swerv_default_config_input.yml" exited with an error code. See stderr for details.

Thanks!

zhanjf commented 4 years ago

It seems environment issue. I use anaconda3 and did not install fusesoc under python 3 environment. after source activate py36 and install fusesoc again. it solved.