Verilator compilation fail due to "common_cells/registers.vh" not found

[tomverbeure]

I'm trying to compile run a swervolf simulation from a clean installation, using Verilator 4.033 devel rev v4.032-73-gdef40fa.

Shortly after kicking things off, I get greeted with the following error:

tom@thinkcenter:~/projects/swervolf$ fusesoc run --target=sim swervolf
WARNING: Unknown item compilation_mode in section Xsim
INFO: Preparing ::cdc_utils:0.1-r1
INFO: Downloading fusesoc/cdc_utils from github
INFO: Preparing chipsalliance.org:cores:SweRV_EH1:1.8
INFO: Downloading chipsalliance/Cores-SweRV from github
INFO: Preparing fusesoc:utils:generators:0.1.5
INFO: Downloading fusesoc/fusesoc-generators from github
INFO: Preparing ::jtag_vpi:0-r5
INFO: Downloading fjullien/jtag_vpi from github
INFO: Preparing pulp-platform.org::common_cells:1.20.0
INFO: Downloading pulp-platform/common_cells from github
INFO: Preparing ::simple_spi:1.6.1
INFO: Downloading olofk/simple_spi from github
INFO: Preparing ::uart16550:1.5.5-r1
INFO: Downloading olofk/uart16550 from github
INFO: Preparing ::verilog-arbiter:0-r3
INFO: Downloading bmartini/verilog-arbiter from github
INFO: Preparing ::wb_common:1.0.3
INFO: Downloading fusesoc/wb_common from github
INFO: Preparing pulp-platform.org::axi:0.25.0
INFO: Downloading pulp-platform/axi from github
INFO: Preparing ::wb_intercon:1.2.2-r1
INFO: Downloading olofk/wb_intercon from github
INFO: Preparing ::swervolf:0.7.3
INFO: Generating ::swervolf-intercon:0.7.3
Found master ifu
Found master lsu
Found master sb
Found slave io
Found slave ram
================================================================================
INFO: Generating ::swervolf-swerv_default_config:0.7.3
INFO: Generating ::swervolf-version:0.7.3
INFO: Generating ::swervolf-wb_intercon:0.7.3
Found master io
Found slave rom
Found slave spi_flash
Found slave sys
Found slave uart
================================================================================
INFO: Setting up project

INFO: Building simulation model
verilator -f swervolf_0.7.3.vc --trace -Wno-fatal
%Error: ../src/pulp-platform.org__common_cells_1.20.0/src/isochronous_spill_register.sv:14:10: Cannot find include file: common_cells/registers.svh
   14 | `include "common_cells/registers.svh"
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
        ... Looked in:
             config/common_cells/registers.svh
             config/common_cells/registers.svh.v
             config/common_cells/registers.svh.sv
             ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/common_cells/registers.svh
             ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/common_cells/registers.svh.v
             ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/common_cells/registers.svh.sv
             ../src/jtag_vpi_0-r5/common_cells/registers.svh
             ../src/jtag_vpi_0-r5/common_cells/registers.svh.v
             ../src/jtag_vpi_0-r5/common_cells/registers.svh.sv
             ../src/pulp-platform.org__common_cells_1.20.0/include/common_cells/common_cells/registers.svh
             ../src/pulp-platform.org__common_cells_1.20.0/include/common_cells/common_cells/registers.svh.v
             ../src/pulp-platform.org__common_cells_1.20.0/include/common_cells/common_cells/registers.svh.sv
             ../src/uart16550_1.5.5-r1/rtl/verilog/common_cells/registers.svh
             ../src/uart16550_1.5.5-r1/rtl/verilog/common_cells/registers.svh.v
             ../src/uart16550_1.5.5-r1/rtl/verilog/common_cells/registers.svh.sv
             ../src/wb_common_1.0.3/common_cells/registers.svh
             ../src/wb_common_1.0.3/common_cells/registers.svh.v
             ../src/wb_common_1.0.3/common_cells/registers.svh.sv
             ../src/pulp-platform.org__axi_0.25.0/include/axi/common_cells/registers.svh
             ../src/pulp-platform.org__axi_0.25.0/include/axi/common_cells/registers.svh.v
             ../src/pulp-platform.org__axi_0.25.0/include/axi/common_cells/registers.svh.sv
             ../src/swervolf-intercon_0.7.3/common_cells/registers.svh
             ../src/swervolf-intercon_0.7.3/common_cells/registers.svh.v
             ../src/swervolf-intercon_0.7.3/common_cells/registers.svh.sv
             ../src/swervolf-wb_intercon_0.7.3/common_cells/registers.svh
             ../src/swervolf-wb_intercon_0.7.3/common_cells/registers.svh.v
             ../src/swervolf-wb_intercon_0.7.3/common_cells/registers.svh.sv
             common_cells/registers.svh
             common_cells/registers.svh.v
             common_cells/registers.svh.sv
%Error: ../src/pulp-platform.org__common_cells_1.20.0/src/isochronous_spill_register.sv:71:5: Define or directive not defined: '`FFLARN'
   71 |     `FFLARN(wr_pointer_q, wr_pointer_q+1, (src_valid_i && src_ready_o), '0, src_clk_i, src_rst_ni)
      |     ^~~~~~~
%Error: ../src/pulp-platform.org__common_cells_1.20.0/src/isochronous_spill_register.sv:71:13: syntax error, unexpected '('
   71 |     `FFLARN(wr_pointer_q, wr_pointer_q+1, (src_valid_i && src_ready_o), '0, src_clk_i, src_rst_ni)
      |             ^~~~~~~~~~~~
%Error: ../src/pulp-platform.org__common_cells_1.20.0/src/isochronous_spill_register.sv:73:5: Define or directive not defined: '`FFLARN'
   73 |     `FFLARN(rd_pointer_q, rd_pointer_q+1, (dst_valid_o && dst_ready_i), '0, dst_clk_i, dst_rst_ni)
      |     ^~~~~~~
%Error: ../src/pulp-platform.org__common_cells_1.20.0/src/isochronous_spill_register.sv:76:5: Define or directive not defined: '`FFLNR'
   76 |     `FFLNR(mem_q, mem_d, (src_valid_i && src_ready_o), src_clk_i)
      |     ^~~~~~
%Error: ../src/pulp-platform.org__common_cells_1.20.0/src/isochronous_spill_register.sv:86:3: syntax error, unexpected end
   86 |   end
      |   ^~~
%Error: Cannot continue
Makefile:16: recipe for target 'Vswervolf_core_tb.mk' failed
make: *** [Vswervolf_core_tb.mk] Error 1

[tomverbeure]

I think the issue is caused by an incorrect path?

Verilator is looking here: ../src/pulp-platform.org__common_cells_1.20.0/include/common_cells/common_cells/registers.svh but I have this: ../src/pulp-platform.org__common_cells_1.20.0/include/common_cells/registers.svh

One way or the other, an additional common_cells crept into the search path...

The issue is that ../src/pulp-platform.org__common_cells_1.20.0/src/isochronous_spill_register.sv has the following:

`include "common_cells/registers.svh"

But swervolf_0.7.3.vc contains:

+incdir+../src/pulp-platform.org__common_cells_1.20.0/include/common_cells
-CFLAGS -I../src/pulp-platform.org__common_cells_1.20.0/include/common_cells

Concatenate these 2, and you get common_cells/common_cells twice.

After changing swervolf_0.7.3.vc like this:

+incdir+../src/pulp-platform.org__common_cells_1.20.0/include/
-CFLAGS -I../src/pulp-platform.org__common_cells_1.20.0/include/

and a few other place too (e.g. include/axi -> include), Verilator compiles when I do make in sim_verilator.

But if I then run fusesoc again, swervolf_0.7.3.vc gets overwritten.

I don't know how to fix this the right way...

Tom

[tomverbeure]

I was able to make it compile and simulate by making the following 2 changes:

diff --git a/pulp-platform.org/axi-0.25.0.core b/pulp-platform.org/axi-0.25.0.core
index c596820..a116f26 100644
--- a/pulp-platform.org/axi-0.25.0.core
+++ b/pulp-platform.org/axi-0.25.0.core
@@ -5,6 +5,7 @@ name : pulp-platform.org::axi:0.25.0
 filesets:
   rtl:
     files:
+      - include/dummy : {is_include_file : true}
       - include/axi/assign.svh :  {is_include_file : true, include_path : include}
       - include/axi/typedef.svh :  {is_include_file : true, include_path : include}
       # Source files grouped in levels. Files in level 0 have no dependencies on files in this
diff --git a/pulp-platform.org/common_cells-1.20.core b/pulp-platform.org/common_cells-1.20.core
index 2c32fd5..e6d19a9 100644
--- a/pulp-platform.org/common_cells-1.20.core
+++ b/pulp-platform.org/common_cells-1.20.core
@@ -6,6 +6,7 @@ filesets:
   rtl:
     files:
       - include/common_cells/registers.svh : {is_include_file : true, include_path : include}
+      - include/dummy : {is_include_file : true}
       # Source files grouped in levels. Files in level 0 have no dependencies on files in this package.
       # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0,
       # etc. Files within a level are ordered alphabetically.

[olofk]

Hmm. could it be that the include_path attribute was introduced in Edalize 0.2.2 and you're using an older version? If so, sorry about that. I should have written down the minimum tool versions somewhere (it would also be doubly embarrassing in the light of https://github.com/olofk/corescore/issues/19)

[tomverbeure]

This is the same machine, so edalize 0.2.3 is already installed.

Tom

[olofk]

Ok, I have another theory now. Is FuseSoC older than version 1.11? Because that was the version that introduced support for include_path. Without that, I think there will be the errors you describe

[tomverbeure]

Updating to version 1.12 fixed it.

Is there a way in the .core file to specify a minimum fusesoc version?

[olofk]

Not at this point. We need to take a look at versioning in more detail. Just adding a minimum FuseSoC version isn't perfect since the core description files are intended to be used by other tools as well. Might be better to add a minor version to the CAPI instead so that FuseSoC and other tools can detect if it encounter core description files written for a a newer API version than it can handle.

In this particular case I just added a note about the minimum FuseSoC version to the readme and filed https://github.com/chipsalliance/Cores-SweRVolf/issues/33 for the general case

[tomverbeure]

Sounds good!

Closing...