fusesoc run --target=sim swervolf with verilator 4.104

[nicolast0604]

INFO: Building simulation model verilator -f swervolf_0.7.3.vc --trace -Wno-fatal %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:58:31: Define or directive not defined: 'RV_LSU_NUM_NBLOAD_WIDTH' 58 | logic [RV_LSU_NUM_NBLOAD_WIDTH-1:0] tag; | ^~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:76:31: Define or directive not defined: 'RV_BTB_ADDR_HI' 76 | logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] index; | ^~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:76:47: Define or directive not defined: 'RV_BTB_ADDR_LO' 76 | logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] index; | ^~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:76:46: syntax error, unexpected ':', expecting TYPE-IDENTIFIER 76 | logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] index; | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:79:31: Define or directive not defined: 'RV_BHT_GHR_RANGE' 79 | logic [RV_BHT_GHR_RANGE] fghr; | ^~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:79:48: syntax error, unexpected ']', expecting TYPE-IDENTIFIER 79 | logic [RV_BHT_GHR_RANGE] fghr; | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:86:31: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 86 | logic [RV_BTB_BTAG_SIZE-1:0] btag; | ^~~~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:87:24: syntax error, unexpected '}' 87 | } br_pkt_t; | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:94:31: Define or directive not defined: 'RV_BTB_ADDR_HI' 94 | logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] index; | ^~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:94:47: Define or directive not defined: 'RV_BTB_ADDR_LO' 94 | logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] index; | ^~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:94:46: syntax error, unexpected ':', expecting TYPE-IDENTIFIER 94 | logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] index; | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:96:31: Define or directive not defined: 'RV_BHT_GHR_RANGE' 96 | logic [RV_BHT_GHR_RANGE] fghr; | ^~~~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:96:48: syntax error, unexpected ']', expecting TYPE-IDENTIFIER 96 | logic [RV_BHT_GHR_RANGE] fghr; | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:103:24: syntax error, unexpected '}' 103 | } br_tlu_pkt_t; | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:112:31: Define or directive not defined: 'RV_BTB_ADDR_HI' 112 | logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] index; | ^~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:112:47: Define or directive not defined: 'RV_BTB_ADDR_LO' 112 | logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] index; | ^~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:112:46: syntax error, unexpected ':', expecting TYPE-IDENTIFIER 112 | logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] index; | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:121:31: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 121 | logic [RV_BTB_BTAG_SIZE-1:0] btag; | ^~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:122:31: Define or directive not defined: 'RV_BHT_GHR_RANGE' 122 | logic [RV_BHT_GHR_RANGE] fghr; | ^~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:122:48: syntax error, unexpected ']', expecting TYPE-IDENTIFIER 122 | logic [RV_BHT_GHR_RANGE] fghr; | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:128:24: syntax error, unexpected '}' 128 | } predict_pkt_t; | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:335:1: syntax error, unexpected endpackage 335 | endpackage | ^~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:142:8: Define or directive not defined: 'TEC_RV_ICG' 142 | module TEC_RV_ICG | ^~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:143:3: syntax error, unexpected '(', expecting IDENTIFIER or TYPE-IDENTIFIER or randomize 143 | ( | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:145:4: syntax error, unexpected output 145 | output Q | ^~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:151:4: syntax error, unexpected assign 151 | assign enable = E | TE; | ^~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:179:4: Define or directive not defined: 'TEC_RV_ICG' 179 | TEC_RV_ICG clkhdr ( .*, .E(en), .CP(clk), .Q(l1clk)); | ^~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:179:23: syntax error, unexpected '(', expecting IDENTIFIER or randomize 179 |TEC_RV_ICG clkhdr ( ., .E(en), .CP(clk), .Q(l1clk)); | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:198:4: Define or directive not defined: 'TEC_RV_ICG' 198 |TEC_RV_ICG rvclkhdr ( ., .E(en), .CP(clk), .Q(l1clk)); | ^~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:198:25: syntax error, unexpected '(', expecting IDENTIFIER or randomize 198 | TEC_RV_ICG rvclkhdr ( .*, .E(en), .CP(clk), .Q(l1clk)); | ^ | ^~~~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:401:24: Define or directive not defined: 'RV_BTB_ADDR_HI' 401 | assign hash = {(pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:401:40: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 401 | assign hash = {(pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:401:58: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 401 | assign hash = {(pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:401:76: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 401 | assign hash = {(pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:401:94: Define or directive not defined: 'RV_BTB_ADDR_HI' 401 | assign hash = {(pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:401:93: syntax error, unexpected ':', expecting TYPE-IDENTIFIER 401 | assign hash = {(pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+1] ^ | ^ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:401:110: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 401 | assign hash = {(pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:401:128: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 401 | assign hash = {(pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:402:23: Define or directive not defined: 'RV_BTB_ADDR_HI' 402 | pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:402:39: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 402 | pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:402:57: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 402 | pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:402:75: Define or directive not defined: 'RV_BTB_ADDR_HI' 402 | pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:402:91: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 402 | pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE+1] ^ | ^~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:403:23: Define or directive not defined: 'RV_BTB_ADDR_HI' 403 | pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+1])}; | ^~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:403:39: Define or directive not defined: 'RV_BTB_BTAG_SIZE' 403 | pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+1])}; | ^~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:403:57: Define or directive not defined: 'RV_BTB_ADDR_HI' 403 | pc[RV_BTB_ADDR_HI+RV_BTB_BTAG_SIZE:RV_BTB_ADDR_HI+1])}; | ^~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:418:39: Define or directive not defined: 'RV_BTB_ADDR_HI' 418 | output logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] hash | ^~~~~~~~~~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:418:55: Define or directive not defined: 'RV_BTB_ADDR_LO' 418 | output logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] hash | ^~~~~~~ %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:418:54: syntax error, unexpected ':', expecting TYPE-IDENTIFIER 418 | output logic [RV_BTB_ADDR_HI:RV_BTB_ADDR_LO] hash | ^ %Error: Exiting due to too many errors encountered; --error-limit=50 Makefile:16: recipe for target 'Vswervolf_core_tb.mk' failed make: *** [Vswervolf_core_tb.mk] Error 1 ERROR: Failed to build ::swervolf:0.7.3 : 'make' exited with an error code

[Johnmc104]

I have the same problem when i reinstall fusesoc, it works

[nicolast0604]

Yes, after re-install fusesoc, it works the same as you.