chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
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support for Riviera-PRO #6

Closed dawidzim closed 4 years ago

dawidzim commented 4 years ago

Hey! This is pull request with support for Riviera-PRO. To fully work need to:

olofk commented 4 years ago

Thanks for this. I have addressed the PRs for Edalize and axi_node now. For SweRV we can solve this with a FuseSoC patch until the fix is upstreamed. Will get back when I have fixed that

olofk commented 4 years ago

ok, I pulled in the SweRV fix as a patch in the core file

If you can verify that it works and change this PR to set compilation_mode directly in the core file, I am happy to pull it in

olofk commented 4 years ago

Fantastic! Squashed and merged. Many thanks for your support