SweRV EL2 with External Sram memory issue

[nimra471]

Hi, I am going to do ASIC of SweRV EL2 for that I am using SRAM as a external memory with a memory controller (axi2mem sram adapter) but I am facing a issue during fetching instruction, core is fetching the instruction only at the starting address of the instruction which is 0000000 and remain same at all the cycle. The above pictures shows the simulation of SweRV EL2 in which at the dout0 sram signal , only 2 3 instruction is reading In he second picture . the ifu_axi_aradder is not incremented and not getting ifu_axi_rvalid. Where as it is working fine with blockRAM on fpga using xilinx ip block memory generator Here is https://github.com/merledu/Rev-Soc-ASIC.git instantiate SRAM in the design/Rev-top

[olofk]

It doesn't look like you are using SweRVolf but some custom SoC that uses the EL2 CPU, so I'm afraid I can't help you with this.