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chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
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added missing compilation mode in core #7

Closed dawidzim closed 4 years ago

dawidzim commented 4 years ago

Hey! Yesterday I forgot to add one compilation mode in core file, here is fix for this

olofk commented 4 years ago

All good. Thanks!