Fix comment for register addresses in syscon

chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

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Closed cdhmanning closed 4 months ago

cdhmanning commented 4 months ago

I'm pretty sure this should be 0x33, not 0x3F.

olofk commented 4 months ago

I think you are absolutely right. Thanks for the fix. Picked and pushed!