chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
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Write Buffer coalescing in compliance tests #8

Closed Podgorny98 closed 2 years ago

Podgorny98 commented 4 years ago

When riscv-gnu-toolchain is built as "rv32imc" following set of rv32i riscv-compliance tests falls on comparing output signature files to reference files:

It happens due to Write Buffer coalescing on print - these tests pass if WB coalescing disable bit is set in the mfdc register .

Reset value equal to 1 in the mrac register for memory regions with side-effects may be a solution.

Podgorny98 commented 4 years ago

I'll try to provide fix

olofk commented 4 years ago

Thanks for reporting. Setting mrac to 1 sounds like the correct solution. It doesn't look like we can set a reset value for the register so we should do this early in the software instead. Perhaps the best way would be to do this as the first operation in the bootloader.

In that case we need to change it in two places.

  1. The standard bootloader. This is normally used when we're building for FPGAs. In this case the program starts here https://github.com/chipsalliance/Cores-SweRVolf/blob/master/sw/boot_main.S#L33 and we could just insert a write to mrac before anything else happens
  2. When we're running simulations, we normally run without a bootloader, and this https://github.com/chipsalliance/Cores-SweRVolf/blob/master/tb/swervolf_core_tb.v#L78 lines is written to the boot ROM (jump to address zero). We could insert the mrac write here before the jump
olofk commented 2 years ago

The bootloader now sets mrac since a while back. Closing this. Please reopen if issue remains