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chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2
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Verilog testbench updated to support newer jtag_vpi:0-r5. #9

Closed JanMatCodasip closed 4 years ago

JanMatCodasip commented 4 years ago

This pull request contains updates in the Verilator testbench, as needed to adopt newer jtag_vpi:0-r5.

The changes shall be used together with: https://github.com/fjullien/jtag_vpi/pull/7

olofk commented 4 years ago

Is this one ready to go in? I won't change the version number though. I found a bug in the version handling, so I will need to go straight to 0.7, and then fix this bug. And before I release 0.7 I have a couple of other things I need to get done first. Most of this is done so I hope to have it ready this week

JanMatCodasip commented 4 years ago

@olofk - This merge request is ready to go in as soon as 0-r5 version of jtag_vpi becomes available. Feel free to include this change to any version of SweRVolf - as convenient.

olofk commented 4 years ago

Thanks for this! Picked and pushed (minus the version change)