AXI4 0.8 DV randomization for POC modes

[nijgit]

0.8 DV script runs fixed configuration does not include randomization can you include this please. If you have this script running on Phy2Phy we can use this.

One-text file will address AIB integration can reuse the same randomization script with AIB.

Also, please send us the randomization results.

[johna-eximiusdesign]

Hey Nij,

This is in the opposite direction of what was discussed with Terry and the rest of the DV team. Eximius had developed a script to randomize the LLINK *.cfg files (used to generate the AXI RTL) and also generate a consistent config_define.svi used by the testbench. 

However, as Divyang said in the e-mail exchange, this was backed out to prepare for the new agreed upon "one text file" flow starts with a text file to generate the aximm_ll.cfg, config_define.svi and other files for AIB. This input "one text file" is then to be randomized according to the test parameters (i.e. AXIMM width, AIB channels, Rates, etc). The randomization scripts may conceptually be similar, but are not interchangeable.

In the meantime, we are manually randomizing the .cfg/.svi files to confirm our testbench will work with various configurations from the "one text file" and in parallel developing the "one text file" randomization script to produce legitimate configurations.

Note that for the POC, there is not much movement available for the marker location (gen1). Strobe can be randomized and the monitor to check strobe locations is working, but with the integration of the CA, there are new configurations required for the CA. Those are spelled out in the "one text file" but are not checked in yet.

[nij-intel]

you can mark this fixed once the yellow-oval is integrated and able to run all UVM tests

[nij-intel]

Let me know if this is supposed to work in 0.8.6 or this is work in progress still.

ran this: python3 run_all_sim.py copy -d sim_test_copy -cfg sailrock_cfg.txt

with the edits on DESIGNWARE_HOME and PROJ_DIR

and did a run_sim ../sim_test_copy

SImulation did not complete with a overnite run:

axi_cyc_cnt_n = 21 @ 2100000000 ps axi_cyc_cnt_n = 22 @ 2200000000 ps axi_cyc_cnt_n = 23 @ 2300000000 ps UVM_WARNING /vip/svt/amba_svt/R-2020.09/axi_slave_svt/sverilog/src/vcs/svt_axi_slave.uvm.svp(532) @ 2304022000: uvm_test_top.axi_env.axi_system_env.slave[0].driver [manage_objections] Timed out due to bus inactivity(bus_inactivity_timeout='d256000). Dropping all objections UVM_WARNING /vip/svt/amba_svt/R-2020.09/axi_master_svt/sverilog/src/vcs/svt_axi_master.uvm.svp(572) @ 2307382000: uvm_test_top.axi_env.axi_system_env.master[0].driver [manage_objections] Timed out due to bus inactivity(bus_inactivity_timeout='d256000). Dropping all objections axi_cyc_cnt_n = 24 @ 2400000000 ps axi_cyc_cnt_n = 25 @ 2500000000 ps UVM_WARNING /vip/svt/amba_svt/R-2020.09/axi_slave_svt/sverilog/src/vcs/svt_axi_slave.uvm.svp(532) @ 2560022000: uvm_test_top.axi_env.axi_system_env.slave[0].driver [manage_objections] Timed out due to bus inactivity(bus_inactivity_timeout='d256000). Dropping all objections UVM_WARNING /vip/svt/amba_svt/R-2020.09/axi_master_svt/sverilog/src/vcs/svt_axi_master.uvm.svp(572) @ 2563382000: uvm_test_top.axi_env.axi_system_env.master[0].driver [manage_objections] Timed out due to bus inactivity(bus_inactivity_timeout='d256000). Dropping all objections

[nij-intel]

Additional information: I am not able to see AXI signals randomized on UVM TB from 0.8.8

[johna-eximiusdesign]

This looks alot like the directed test case in AXI-MM, which doesn't have much (if any) randomization. Can you run the random_wr_rd_test. That is where the randomization is in full effect.

[johna-eximiusdesign]

Flow control (in addition to the other randomization) has been added and tuned in 0.8.9

[nij-intel]

0.8.9 status:

a. Mode1 – AXI4-MM – 2Channel (rdata==0 issue). Likely on Mode4 as well. b. Mode2 – AXI4-Stream – 2-Channel (with TLAST and TKEEP) – VIP differences – fails with 2021.9, passes with 2021.6 c. Mode3 – AXI4-Stream – 7 channel (align_done and align_err issue) d. Mode4 – AXI4-MM – 1 channel – TBD

[nij-intel]

Mode1: workaround VIP for rdata==0. Might need Synopsys help to configure the VIP right. Mode2 - Nij to create 2 different run setup for 2021.6 and 2021.9 for Synopsys discussion. Not critical for 0.8 because we have a working version Mode3 - fix is expected in the next update - configuration issue between DV and CA Mode4 - bypassing CA - work in progress

[johna-eximiusdesign]

8.11 drop update: Mode 4 is working Mode 3 is proving difficult for DV (hard to send a strobe from a F,H,Q clock to a F,H,Q clock and have any consistency), but we're close. We can see the RTL is good and if we make custom USER strobe generators, it works, but so far we have not found single USER generator that works for all combinations. Mode 2 sounds like with different VIP version, it is passing. We are pursuing with Synopsys. Mode 1 (rdata == 0) is WIP

[nij-intel]

Things to check:

1. AXI4 rdata==0
2. flow control randomization

[nij-intel]

update from 0.8.11 on rdata and flow control

[johna-eximiusdesign]

Updated in 8.12. W and R flow control should be checked in. We'll likely need a second test to create sufficient stress on the AW, AR, B busses. It should be noted that the flow control slows down the simulations considerably.

RDATA random has been proving tricky. Current version randomizes the lower 32 bits only. Locally, we have a "walking 32 bit" (i.e. in 64 bit data, lower then upper word are randomized). Working with Synopsys FAE to improve randomness.

[nij-intel]

I am able to reproduce what you see

[johna-eximiusdesign]

RDATA should be randomized as part of 0.8.13

[nij-intel]

On my end it appears to be partially randomized still

[johna-eximiusdesign]

Sorry. My mistake. It was there, but it was backed out before I pulled the repo. The flow control changes were causing the sims to take excessively long, so we reverted to an earlier version, which ended up dropping the RDATA randomization. It should be in the next drop.

[johna-eximiusdesign]

0.8.15 drop should have RDATA randomization (actually 0.8.14 had it... forgot to update this issue)

[nij-intel]

Discussed strobe generation difference between ST-64 and St-256 testcases, attaching it here for reference

[johna-eximiusdesign]

0.8.16 update

• Strobe difference was fixed
• Random flow control is enabled, but not cleanly scripted. Adding one `define will enable it. Details on how to do this below.
• RDATA is fully randomized (has been fixed for a couple of revs). But this can only be seen in the directed_test.

To enable random flow control, open the Makefile, and add +define+AXIMM_FLOWCNT right after ${comp_define} in comp_top target (around line 179), you will see the flow control for all 5 AXI channels are stressed in random_wr_rd_test test (as well as other tests). Subsequent scripting changes will be made to make this optional. It seems obvious, but flow control slows down the logic and will increases simulation time, which is why it is not on by default.

[johna-eximiusdesign]

Marking as fixed as this covers the known issues.

[nij-intel]

Getting a new error for llink/dv/aximm/tb_mh2.1_sh1_64

Error-[XMRE] Cross-module reference resolution error /0.8.16/try/llink/dv/aximm/hdl_interconnect/ca_connect.svi, 107 Error found while trying to resolve cross-module reference. token 's_rx_align_done'. Originating module 'aximm_DUT_wrapper', first module hit 'aximm_top_tb'. Source info: .ax (aib_mac_if_s0.s_rx_align_done[0]) Instance stack trace: aximm_DUT_wrapper
/nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.8.16/try/llink/dv/aximm/tb/aximm_top_tb.sv, 118 aximm_top_tb
/nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.8.16/try/llink/dv/aximm/tb/aximm_top_tb.sv, 46

[johna-eximiusdesign]

This popped up for us too... it is related to the delay signals Terry added, but I cannot explain why the failure popped up more recently (my only guess is with all the `ifdefs, it wasn't being used before).

You can try 0.8.17 we just uploaded, where I think we may have fixed that. otherwise, the fix was pretty simple... but it was hard to find with all of the `include sections of code.

On Thu, Nov 11, 2021 at 2:28 PM nij-intel @.***> wrote:

Getting a new error for llink/dv/aximm/tb_mh2.1_sh1_64

Error-[XMRE] Cross-module reference resolution error /0.8.16/try/llink/dv/aximm/hdl_interconnect/ca_connect.svi, 107 Error found while trying to resolve cross-module reference. token 's_rx_align_done'. Originating module 'aximm_DUT_wrapper', first module hit 'aximm_top_tb'. Source info: .ax (aib_mac_if_s0.s_rx_align_done[0]) Instance stack trace: aximm_DUT_wrapper

/nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.8.16/try/llink/dv/aximm/tb/ aximm_top_tb.sv, 118 aximm_top_tb

/nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.8.16/try/llink/dv/aximm/tb/ aximm_top_tb.sv, 46

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[nij-intel]

rdata looks ok now, AR and AW not randomized?

[johna-eximiusdesign]

I'm not sure what you are saying. The image you posted clearly shows fields like arsize, arlen, araddr, awid, awsize, awlen and others changing from iteration to iteration. So why are you suggesting they are not randomized?

[johna-eximiusdesign]

Release 0.9.0. Flow control randomization documented better. AFAIK, everything above should be in this version. Marking as fixed.

[nij-intel]

With +define+AXIMM_FLOWCNT AR and AW shows same behavior as 0.8.17

[nij-intel]

Can we add AXIMM_FLOWCNT to the makefile/script?

[nij-intel]

with ./run_sim SCENARIO=random_wr_rd_test FLOWCONTROL=AXIMM_FLOWCNT results look better