CA delay modeling

[nij-intel]

We need to model AIB channel delay to introduce delay in DV to test CA deskew capability

There are 2 approaches:

1. Use aib_tx_rd_delay and aib_rx_rd_delay on per channel

                                                  Value

aib_tx_rd_delay 3-6 aib_rx_rd_delay 3-6

For each channel you will add tx+rx for deskew. Per channel delay can be randomized (done in yo)

this provides a range of 6-12 delay on each channel or a max of 6 clock cycles of channel to channel skew

this delay should be coherent with master_sl/ms_tx_transfer_en and slave_sl/ms_tx_transfer_en delay for correct operation since these controls are used fo TX_online and RX_online.

2. Use separate parameter on PHY to MAC side to model the delay and make it coherent with master_sl/ms_tx_transfer_en and slave_sl/ms_tx_transfer_en from a delay standpoint.

For 0.8 we will be using approach 1, we are investigating approach 2 for 1.0 usage.

[nij-intel]

Assigning this to Eximius to update the status on integration and report stress test results.

[johna-eximiusdesign]

AXIMM, AXIST and CA all have the upgraded channel delays provided by Terry.

AXIMM, AXIST have upgraded to determine the randomness from the SEED and sailrock.cfg, where the original relies on an external "third party" csh to generate the delay constraints. CA will be upgraded soon, but I'm marking this as fixed since the baseline delays are in place as of 0.8.17.

[johna-eximiusdesign]

Upgrading the CA TB to use the new inter skew from sailrock.

[johna-eximiusdesign]

Release 0.9.0 has updated skew format in place for CA as well.

[nij-intel]

Was able to use 7 channel AXI4-Stream design to test the CA delay with these values:

GLOBAL_INTER_CH_SKEW_S2M 0x08060504030201 GLOBAL_INTER_CH_SKEW_M2S 0x00020304050608

CA_FIFO_DEPTH 8 8 8,16,32 Configured by setting CA parameter AD_WIDTH = Log2Depth