chipsalliance / aib-protocols

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axi4-mm addr width cover point not correct #81

Closed nij-intel closed 2 years ago

nij-intel commented 2 years ago

covergroup aximm_cov; aximm_datawidth_cov : coverpoint aximm_cov_datawidth { bins aximm_datawidth_bin[] = {32,64,128,256,512}; } aximm_addrwidth_cov : coverpoint aximm_cov_addrwidth { bins aximm_addrwidth_bin[] = {32,64,128,256,512}; }

I think this should {32,48} can you please review rest of the cover points to make sure it is aligning with DUT

johna-eximiusdesign commented 2 years ago

Fixed in 0.9.8 drop

nij-intel commented 2 years ago

aximm_addrwidth_cov : coverpoint aximm_cov_addrwidth { bins aximm_addrwidth_bin[] = {32,64}; }

should include 48?

johna-eximiusdesign commented 2 years ago

This issue should be fixed in the Feb 18 release.

nij-intel commented 2 years ago

fixed in 1.0