Top level module ports

[steven-bellock]

Caliptra's top level module currently exposes https://github.com/chipsalliance/caliptra-rtl/blob/d334c84a0e513a3d66a51078f020a414a2c86a67/src/integration/rtl/caliptra_top.sv#L72 https://github.com/chipsalliance/caliptra-rtl/blob/d334c84a0e513a3d66a51078f020a414a2c86a67/src/integration/rtl/caliptra_top.sv#L109 which means that for folks that are integrating Caliptra into a VHDL/Verilog/SystemC/etc environment they may need to make a wrapper that breaks out the interface into simpler ports. Rather than requiring the Integrator to do this, Caliptra could provide a "standard" wrapper that just exposes logic ports, which should be directly instantiable in a VHDL/Verilog/SystemC environment.

[bharatpillilli]

Its been few months since ports are frozen - no change right now unless its a showstopper as we are 3 weeks from 1p0

[steven-bellock]

Yeah it's not a showstopper, just a quality-of-life enhancement. If Caliptra is being instantiated in a SystemVerilog environment then the Integrator can use the full-featured module one level down.