DFT issue: Scan Mux not present in the following reset path

[saidheeraj111]

Hi Bharat and Team, Can you please check this DFT issue observed during caliptra schematic debug using spyglass tool. I have already sent a mail to caliptra work group. Please find the below error snapshot where scan mux is missed.

Thanks, K. Dheeraj Reset_path_issue.docx

[saidheeraj111]

Hi Bharat, Can you please let us know the fix as quickly as possible.

Thanks, K. Dheeraj

[amullick007]

Hi @bharatpillilli,

Looks like we would need DFT overrides on both _cptra_uc_rstb and _cptra_noncore_rstb before they are consumed.

caliptra_top.soc_ifc_top1.i_soc_ifc_boot_fsm.cptra_uc_rst_b caliptra_top.soc_ifc_top1.i_soc_ifc_boot_fsm.cptra_noncore_rst_b

I remember we had a discussion over DFT override logic inside veer core. However these resets are consumed by logic outside veer core as well and hence we should add the override logic inside Boot FSM before sending it out.

Regards, Avirup

[saidheeraj111]

Hi Narasimha/Prasanna, The below mail is reply from the caliptra team. Seems they are talking about the DFT logic insertion. But they haven’t mentioned the date. So, based on this proceed further.

Thanks, K. Dheeraj.

From: amullick40412 @.> Sent: Tuesday, August 15, 2023 11:56 PM To: chipsalliance/caliptra-rtl @.> Cc: Kakaraparthi Venkata siva sai Dheeraj @.>; Author @.> Subject: Re: [chipsalliance/caliptra-rtl] DFT issue: Scan Mux not present in the following reset path (Issue #175)

[Warning..! EXTERNAL Mail]: This message was sent from outside of Synapse Design. Please do not click links or open attachments unless you recognize the source of this email and know the content is safe. Please report all suspicious emails to @.**@.>" as an attachment.

Hi @bharatpillillihttps://github.com/bharatpillilli,

Looks like we would need DFT overrides on both cptra_uc_rst_b and cptra_noncore_rst_b before they are consumed.

caliptra_top.soc_ifc_top1.i_soc_ifc_boot_fsm.cptra_uc_rst_b caliptra_top.soc_ifc_top1.i_soc_ifc_boot_fsm.cptra_noncore_rst_b

I remember we had a discussion over DFT override logic inside veer core. However these resets are consumed by logic outside veer core as well and hence we should add the override logic inside Boot FSM before sending it out.

Regards, Avirup

— Reply to this email directly, view it on GitHubhttps://github.com/chipsalliance/caliptra-rtl/issues/175#issuecomment-1679398368, or unsubscribehttps://github.com/notifications/unsubscribe-auth/BAYJH6C3TXRESN4QXFV2E3LXVO5KPANCNFSM6AAAAAA3F35FIU. You are receiving this because you authored the thread.Message ID: @.***>

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[saidheeraj111]

• Rahul

From: Kakaraparthi Venkata siva sai Dheeraj @.> Sent: Wednesday, August 16, 2023 10:00 AM To: chipsalliance/caliptra-rtl @.>; chipsalliance/caliptra-rtl @.> Cc: Author @.>; Katakam Narasimharao @.>; Prasanna Choudhary @.> Subject: RE: [chipsalliance/caliptra-rtl] DFT issue: Scan Mux not present in the following reset path (Issue #175)

Hi Narasimha/Prasanna, The below mail is reply from the caliptra team. Seems they are talking about the DFT logic insertion. But they haven’t mentioned the date. So, based on this proceed further.

Thanks, K. Dheeraj.

From: amullick40412 @.**@.>> Sent: Tuesday, August 15, 2023 11:56 PM To: chipsalliance/caliptra-rtl @.**@.>> Cc: Kakaraparthi Venkata siva sai Dheeraj @.**@.>>; Author @.**@.>> Subject: Re: [chipsalliance/caliptra-rtl] DFT issue: Scan Mux not present in the following reset path (Issue #175)

[Warning..! EXTERNAL Mail]: This message was sent from outside of Synapse Design. Please do not click links or open attachments unless you recognize the source of this email and know the content is safe. Please report all suspicious emails to @.**@.>" as an attachment.

Hi @bharatpillillihttps://github.com/bharatpillilli,

Looks like we would need DFT overrides on both cptra_uc_rst_b and cptra_noncore_rst_b before they are consumed.

caliptra_top.soc_ifc_top1.i_soc_ifc_boot_fsm.cptra_uc_rst_b caliptra_top.soc_ifc_top1.i_soc_ifc_boot_fsm.cptra_noncore_rst_b

I remember we had a discussion over DFT override logic inside veer core. However these resets are consumed by logic outside veer core as well and hence we should add the override logic inside Boot FSM before sending it out.

Regards, Avirup

— Reply to this email directly, view it on GitHubhttps://github.com/chipsalliance/caliptra-rtl/issues/175#issuecomment-1679398368, or unsubscribehttps://github.com/notifications/unsubscribe-auth/BAYJH6C3TXRESN4QXFV2E3LXVO5KPANCNFSM6AAAAAA3F35FIU. You are receiving this because you authored the thread.Message ID: @.**@.>>

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[Nitsirks]

Qualified generated resets with scan mode so that we don't incidentally reset flops during scan mode.

assign cptra_noncore_rst_b = cptra_noncore_rst_b_nq | scan_mode; assign cptra_uc_rst_b = cptra_uc_rst_b_nq | scan_mode;