Global hdlin variable hazard: hdlin_interface_port_downto true

[nstewart-amd]

Source: ahb_lite_bus.sv

https://spdocs.synopsys.com/dow_retrieve/qsc-t/dg/dcolh/T-2022.03/dcolh/Default.htm#manpages/synn/ELAB.htm#ELAB-123 https://solvnetplus.synopsys.com/s/article/How-Does-Elaboration-Represent-Arrays-of-Interfaces-1576165809529

Two options:

1. Configuring our synth environment with: hdlin_interface_port_downto true Global impact to all RTL file read. Not acceptable.

2. Change the port ordering in ahb_lite_bus.sv. See modified RTL here. Trial in progress: ahb_lite_bus.sv.tar.gz

[nstewart-amd]

Code change provided resolved the ELAB-123 Error.