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chipsalliance / caliptra-rtl

HW Design Collateral for Caliptra RoT IP
Apache License 2.0
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Caliptra Synthesis Errors #317

Closed amullick007 closed 3 weeks ago

amullick007 commented 9 months ago

We are getting below synthesis errors with latest RTL.

Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[6]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[5]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[4]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[3]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[2]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[1]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[0]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)

Upon checking the RTL, I saw that _perf_datff.din[6:0] is connected to _ifu_ic_rw_int_addrff[12:6]. The driver of _ifu_ic_rw_int_addrff is coming from below module code which is disabled because _pt.ICACHEENABLE is 0.

         rvdffie #(pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO+pt.ICACHE_NUM_WAYS+1) tag_addr_ff (.*,
                                                                                              .clk(free_l2clk),
                                                                                              .din({ifu_ic_rw_int_addr_w_debug[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO],
                                                                                                    ifu_tag_wren_w_debug[pt.ICACHE_NUM_WAYS-1:0],
                                                                                                    ic_valid_w_debug}),
                                                                                              .dout({ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO],
                                                                                                     ifu_tag_wren_ff[pt.ICACHE_NUM_WAYS-1:0],
                                                                                                     ic_valid_ff})
                                                                                              );

Is it ok for synthesis to treat the input din of _perr_datff as 0?

Nitsirks commented 9 months ago

Yes, it has no loads that I can find with icache disabled.

We're adding moving this flop to a list of requests for VeeR team to implement.

amullick007 commented 7 months ago

@Nitsirks Is this issue resolved in RTL1.0 release?

Nitsirks commented 7 months ago

No. Looks like there is a PR out for VeeR that will fix it. I assume we'll absorb this for 1.1

https://github.com/chipsalliance/Cores-VeeR-EL2/issues/149

amullick007 commented 7 months ago

Thanks Michael, do you know the approximate timeline for 1.1 release?

bharatpillilli commented 5 months ago

@Nitsirks - close this?

calebofearth commented 3 weeks ago

Fixed for 1.1 release in 020cdc6 via #483