Sequential transfers with more than single burst type.

chipsalliance / caliptra-rtl

HW Design Collateral for Caliptra RoT IP

Apache License 2.0

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Sequential transfers with more than single burst type. #367

Closed tnsri closed 10 months ago

tnsri commented 10 months ago

Hi,

can you please confirm if we have a senario which covers sequential transfers with more than single burst type.

Thanks, Navya

tnsri commented 10 months ago

HTRANS->Sequential HBURST->More than single burst

Nitsirks commented 10 months ago

No, our microcontroller only supports non-sequential single burst transactions.

RJMJJJ commented 10 months ago

Is this limitation because of the pending_hsel logic in AHB-L decoder?

Nitsirks commented 10 months ago

No, hburst is hardwired to 0b000 in the VeeR core.

RJMJJJ commented 10 months ago

Is there any other version of source code available or any guidelines that can be provided to make hburst supporting more than single burst?

Thanks

Nitsirks commented 10 months ago

No there is not.

Do you have a particular concern? The AHB bus is entirely internal to Caliptra, only ROM and FW are exposed to it.

RJMJJJ commented 10 months ago

We were exploring for adding any other peripheral supporting multi-beat burst mode for the RISC-V access on the AHB-L interconnect.

Nitsirks commented 10 months ago

Adding peripherals to Caliptra is not a valid use case of Caliptra IP.

RJMJJJ commented 10 months ago

I understand current Caliptra 1.0 is Passive Mode, but if to use it in Active Mode QSPI/UART peripherals will be required to be accessed directly by Caliptra RISC-V, exploring same. With these peripherals added at least for QSPI multi-beat burst mode will be required.