Release 1.1 sign-off checklist

calebofearth commented 7 months ago

Overview

This issue tracks the outstanding items to complete prior to finalizing the 1.1 release version, and provides public visibility to the sign-off protocol used for releases. Discussions among contributors have been ongoing to agree on the proposed changes in any outstanding Pull Requests, in order to converge all required tests and sign-off protocols.

Checklist

[x] Regressions sign-off from Microsoft (after finalizing all PRs) @calebofearth
[x] Coverage sign-off @calebofearth
[x] FPGA validation (Luke Mahowald)
[x] Update HW Rev ID, HW_CONFIG registers @calebofearth
[x] Complete Lint review @nstewart-amd
[x] Complete CDC review @nstewart-amd
[x] Complete RDC review @amullick007
[x] Formal Verification review @mojtaba-bisheh
[x] Update documentation
- [x] Add revised lint rules to integration specification @nstewart-amd @Nitsirks
- [x] Add CDC constraints to integration specification @nstewart-amd
- [x] Add RDC constraints/waivers to integration specification @amullick007
- [x] Update release notes @calebofearth
- [x] README updates @calebofearth
- [x] Add CDC tool version @nstewart-amd
- [x] Add RDC tool version @amullick007
- [x] Add latest synthesis results to the integration specification @nstewart-amd
[x] Firmware update regarding FIPS compliance and hw requirements @JohnTraverAmd
- NOTE: FIPS compliance pending approval of HMAC384 algorithm instead of HMAC512 - discussion with FIPS WG
[x] Tag the main branch with 1.1 @calebofearth
[x] Create 1.1 branch for FW regression consumption

Pending Pull Requests to complete

[x] https://github.com/chipsalliance/caliptra-rtl/pull/461 (CLOSE do not merge!)
[x] https://github.com/chipsalliance/caliptra-rtl/pull/501 (CLOSE do not merge! Proposed change will not be accepted)
[x] https://github.com/chipsalliance/caliptra-rtl/pull/483
[x] https://github.com/chipsalliance/caliptra-rtl/pull/486
[x] https://github.com/chipsalliance/caliptra-rtl/pull/478
[x] https://github.com/chipsalliance/caliptra-rtl/pull/489
[x] https://github.com/chipsalliance/caliptra-rtl/pull/510
[x] https://github.com/chipsalliance/caliptra-rtl/pull/524
[x] https://github.com/chipsalliance/caliptra-rtl/pull/528
[x] https://github.com/chipsalliance/caliptra-rtl/pull/541
[x] https://github.com/chipsalliance/caliptra-rtl/pull/533
[x] https://github.com/chipsalliance/Caliptra/pull/196
[x] https://github.com/chipsalliance/caliptra-rtl/pull/519
[x] https://github.com/chipsalliance/caliptra-rtl/pull/534
[x] https://github.com/chipsalliance/caliptra-rtl/pull/535
[x] https://github.com/chipsalliance/caliptra-rtl/pull/536
[x] https://github.com/chipsalliance/caliptra-rtl/pull/539
[x] https://github.com/chipsalliance/caliptra-rtl/pull/546
[x] https://github.com/chipsalliance/caliptra-rtl/pull/496

calebofearth commented 7 months ago

@amullick007 : please link to the generate-label PR if you plan to submit it EDIT: added #510 to checklist

calebofearth commented 7 months ago

@nsteward-amd: Please update here on the status/urgency of #446 UPDATE: Resolved

calebofearth commented 7 months ago

Crypto formal verification: Completed by Lubis EDA.

amullick007 commented 7 months ago

Added PR #511 for RDC documentation updates

nstewart-amd commented 6 months ago

1.1 LINT analysis is considered complete.

nstewart-amd commented 6 months ago

1.1 CDC analysis is complete and pass.

nstewart-amd commented 5 months ago

I've added PR's for #534 #535 #536

jlmahowa-amd commented 5 months ago

FPGA tests are passing.

SW repo test for hw_rev needs to be updated for 1.1
Manually checked that BOOT_WAIT flow over JTAG works on FPGA. This is done without CG enabled so might not cover #523.

nstewart-amd commented 5 months ago

Synthesis | Timing | Formality | Stdcell Area | Memory Area | Total Area | Comment -- | -- | -- | -- | -- | -- | -- 1.0 | PASSED | PASSED | 86665 | 239937 | 334473 | 1.1 | -17.18ps (496MHz Achieved) | PASSED | 93418 | 239937 | 341226 | Critical path ICCM SRAM->DCCM SRAM

calebofearth commented 4 months ago

Release 1.1 has been tagged. This issue will remain open pending the final checklist item, https://github.com/chipsalliance/Caliptra/pull/196.

chipsalliance / caliptra-rtl