KAT failed when simulation

[morris-c-mao]

Simulation Env:

• Tried RTL: v1.0 or commit 41b77ba

  • Tried configuration: USER ICG or bypassing clock gating
    1. USER ICG: insert technology specific ICG cell to replace RTL type clock gating.
    2. Bypassing clock gating: use defines to make RTL act as FPGA.

• Tried ROM: v1.0.1 or v1.0.2

Sympton (identical on RTL v1.0 or commit 41b77ba) :

• USER ICG and ROM v1.0.1
  1. First sha256 is finished correctly.
  2. Program Counter keeps jumping back to 0 while doing ROM integrity check.
• USER ICG and ROM v1.0.2
  1. First sha256 is calculated. RV reads results and golden from sha256 controller and ROM, respectively. However RV reports fails in the end.
• Bypass clock gating and ROM v1.0.1
  1. First sha256, ROM integrity check, and second sha256 are finished correctly.
  2. RV reports fail while doing following sha1.
• Bypass clock gating and ROM v1.0.2
  1. First sha256 is calculated. RV reads results and golden from sha256 controller and ROM, respectively. However RV reports fails in the end.
• Skipping KAT
  1. ready_for_fw_push is asserted on any configuration or RTL version.

Description

We are doing RTL/ROM simulation to make sure integration is good and encounter simulation results as above. Besides simulation, we also build Xilinx FPGA. FPGA works with KAT. We think it might not be ROM issue because RV's AHB accesses are as expected. For example, with ROM v1.0.2, RV reads sha256 results from controller and ROM. This is as expected. However the comparing result is NG. Are there something we missed?

BTW, is a new release, like v1.1, coming soon?

[bharatpillilli]

1.1 is tagged a week or so ago. May be ROM+RTL combo you are using?

[morris-c-mao]

We tried v1.1. The symptoms are the same no matter combining with ROM v1.0.1 or v1.0.2.

[morris-c-mao]

Update:

The Fatal Error is because data output from DCCM is not latched by following Flip-Flop correctly. If we change DCCM from real SRAM model fo Flip-Flop type, KAT simulation is passed. Or adding unit delay on SRAM output also helps.

[Nitsirks]

Thanks for the update Morris. The integration spec details the SRAM implementation here, for future reference: https://github.com/chipsalliance/caliptra-rtl/blob/main/docs/CaliptraIntegrationSpecification.md#sram-timing-behavior

[morris-c-mao]

Thanks Nitsirks. The SRAM timing matches document, model or Flip-Flop type. We guess the issue is because of simulation enviornment, maybe our setting or simulator, Cadence Xcelium, itself. We will try Synopsys VCS when we have chance.