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chipsalliance / caliptra-rtl

HW Design Collateral for Caliptra RoT IP
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Add test for JTAG during uC reset #554

Open robertszczepanski opened 4 months ago

robertszczepanski commented 4 months ago

Test for issue https://github.com/chipsalliance/caliptra-rtl/issues/523 resolved by PR https://github.com/chipsalliance/caliptra-rtl/pull/541.

The test flow description:

  1. Initiate Caliptra boot flow from the testbench typical for every test suite. The test suite awaits BOOTFSM_GO register value 0 in a loop.
  2. Connect to Caliptra via JTAG (OpenOCD).
  3. JTAG: Write 0 to BOOTFSM_GO register to ensure uC will not leave reset state unless permitted.
  4. Caliptra SW: Initiate Firmware Update Reset which puts uC in Boot FSM wait state due to BOOTFSM_GO set to 0.
  5. JTAG: Read dmstatus register until uC is in reset state.
  6. JTAG: Write 1 to BOOTFSM_GO register to proceed with boot flow.
  7. Caliptra SW: If reset was successful, write 1 to the mailbox to indicate successful boot.
  8. JTAG: Read the mailbox until it contains 1 and finish the test.

This test has been confirmed to fail before https://github.com/chipsalliance/caliptra-rtl/pull/541/commits/a1a2d697c7e253af5b5a0a57921072fb990ae5ae.