Current FPGA implementation of the logging functionality diverges from other environments. This implementation also introduces a lot of delays as the FW has to wait for the test to read out each byte before continuing to log.
This could be improved by either:
Simplifying the communication and adding a FIFO in HW between Caliptra and the FPGA SOC adapter.
In addition to the byte being written to generic_output_wires, add a bit that toggles when a byte is written.
Add a FIFO to the FPGA to buffer the writes out of Caliptra until the test SW can read it out from the SOC adapter.
Or implementing FW to use Caliptra's actual UART HW.
Current HW has a real UART available to be used. Would require implementation of the UART code in FW and any modifications to the sw-emulator and Verilator implementations to converge the logic.
jlmahowa-amd
commented
1 year ago
Current FPGA implementation of the logging functionality diverges from other environments. This implementation also introduces a lot of delays as the FW has to wait for the test to read out each byte before continuing to log. This could be improved by either:
Simplifying the communication and adding a FIFO in HW between Caliptra and the FPGA SOC adapter. In addition to the byte being written to generic_output_wires, add a bit that toggles when a byte is written. Add a FIFO to the FPGA to buffer the writes out of Caliptra until the test SW can read it out from the SOC adapter.
Or implementing FW to use Caliptra's actual UART HW. Current HW has a real UART available to be used. Would require implementation of the UART code in FW and any modifications to the sw-emulator and Verilator implementations to converge the logic.