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chipsalliance / chisel

Chisel: A Modern Hardware Design Language
https://www.chisel-lang.org/
Apache License 2.0
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Explicit readwrite ports for memories #238

Closed donggyukim closed 1 year ago

donggyukim commented 8 years ago

For now, there's no way to express readwrite ports in Chisel3. In Chisel2, they are inferred from read and write ports by checking their enable signals. I think there should be an explicit way as well as an implicit way to infer in firrtl.

terpstra commented 8 years ago

Strongly agree!

On Jul 21, 2016 1:27 PM, "Donggyu" notifications@github.com wrote:

For now, there's no way to express readwrite ports in Chisel3. In Chisel2, they are inferred from read and write ports by checking their enable signals. I think there should be an explicit way as well as an implicit way to infer in firrtl.

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ducky64 commented 7 years ago

Resolution: there should be an explicit readwrite port for memories,

jackkoenig commented 4 years ago

Wait for https://github.com/freechipsproject/firrtl/pull/1210

jackkoenig commented 1 year ago

This is done in https://github.com/chipsalliance/chisel/pull/3190.