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chipsalliance / chisel

Chisel: A Modern Hardware Design Language
https://www.chisel-lang.org/
Apache License 2.0
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Use verilator VPI interface #331

Open ucbjrl opened 7 years ago

ucbjrl commented 7 years ago

Predicting verilator's signal names is increasingly problematic. #329 (compiling with -O0) breaks the existing harness communication due to signal renaming.

jackkoenig commented 7 years ago

Which harness breaks? The chisel3 tests pass using their testing harness, is it a problem in https://github.com/ucb-bar/chisel-testers?

donggyukim commented 7 years ago

We should move this to chisel-tester.

wallento commented 7 years ago

Hi, actually I think you want to use DPI for it instead of VPI.

donggyukim commented 7 years ago

@wallento Can we access internal signals with DPI?

wallento commented 7 years ago

Yes, you can. It depends a bit on what you want to achieve. Do I understand it correctly it is driving signals in a testbench? Then DPI works fine, VPI has the only advantage that you can mess in the entire hierarchy. DPI instead is the suggested way for ease of use and clarity from my point of view.

wallento commented 7 years ago

If you want to randomly access all signals than VPI (or plain C++) and /* verilator public */ are indeed needed.

oharboe commented 4 years ago

I created a Perl post-processing hack to inject /* verilator public */ after input/output signals that I need to reach from C++. This hack broke with 3.2.0, because the Verilog is very slightly different in 3.2.0.

It would be great if there was a robust way to specify that should /* verilator public */ follow input or output signals to a module in the generated Verilog.

seldridge commented 4 years ago

@oharboe: I don't have an example of doing this, but the DescriptionAnnotation is likely the stable way of doing this coupled with https://github.com/freechipsproject/firrtl/pull/1172. The attributes you're talking about are generally needed...

wallento commented 4 years ago

just a quick update on the verilator side: There will soon be support to specify public signals to be accessed via VPI in a separate file, so you will not need to add the comments to Verilog, but specifiy signals by their path (most probably with wildcards) in a file simply. Cheers!

jackkoenig commented 4 years ago

Thanks for your hard work on this @wallento 🙂