Open isjcliu opened 6 months ago
I have the same problem. Do you find the way to solve this? I find the answer ( #3706 )about this problem saying chisel can only generate systemverilog?
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To avoid the generation of systemverilog syntax like "automatic logic", you can add
firtoolOpts = Array("-lowering-options=disallowLocalVariables")
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chisel5.1.0 firtool 1.4.3 In the source code, the emitverilog function is a systemverilog instead of verilog. I changed it to verilog, but the generated .v file is not available in vivado and contains the syntax of systemverilog