seldridge
commented
9 months ago The SystemVerilog output should be fine for all backend tools. If you need
more control, you can use some of the LoweringOptions here, likely,
enabling disallowLocalVariables to avoid automatic logic. The default
emission option avoids all things which may be controversial, e.g., there
is no always_comb/always_ff emission unless you opt in.
Part of the problem here is that Chisel has constructs which are fundamentally not representable in Verilog. Specifically, Chisel has assert, assume, and cover. Hence, even though Chisel 3.6 was claiming to emit "Verilog", it was emitting SystemVerilog. (As soon as you emit a single SystemVerilog construct, the entire thing is SystemVerilog.) Chisel 5 stops pretending that it was emitting Verilog and calls it what it is.
On Sat, Dec 30, 2023 at 4:54 PM Rei_Fu_Zhang @.***> wrote:
Hi,Sorry for a dummy question , how can I translate my Chisel(3.6.0) codes to only verilog files without systemverilog files when useing emitVerilog!! thanks a lot!!
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Hi,Sorry for a dummy question , how can I translate my Chisel(3.6.0) codes to only verilog files without systemverilog files when useing emitVerilog!! thanks a lot!!