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chipsalliance / chisel

Chisel: A Modern Hardware Design Language
https://www.chisel-lang.org/
Apache License 2.0
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ChiselSim waveforms #4246

Open HakamAtassi opened 3 months ago

HakamAtassi commented 3 months ago

Hello!

I feel like I'm not the first to ask, but I haven't found anything regarding this as an open issue so I'll ask nonetheless.

ChiselSim. Waveforms. Yes or no?

Can I write chisel/scala tests and dump a VCD like ChiselTest?

zhutmost commented 3 months ago

A simple answer is: yes

HakamAtassi commented 3 months ago

A simple answer is: yes

How? Is there a native way of doing that or does it involve tywaves?

zhutmost commented 3 months ago

Enable traceEnabled when yourunElaboratedModule during simulation. See https://github.com/chipsalliance/chisel/blob/8f00067a973ce377440bf16b9a49a4120316217b/src/main/scala/chisel3/simulator/package.scala#L92

And I have some wrapper code to make it much easier. See my example here.

jackkoenig commented 3 months ago

It's not exposed with the existing EphemeralSimulator, but there is work towards simpler user APIs like https://github.com/chipsalliance/chisel/pull/4209 which should make this easier.