PriorityMux drops arguments if input sequences are not the same size

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.5.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.5.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.util.PriorityMux
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class Foo extends Module {
  val a, b, c = IO(Input(Bool()))
  val foo, bar, fizz = IO(Input(UInt(8.W)))
  val out = IO(Output(UInt(8.W)))

  out := PriorityMux(Seq(a, b), Seq(foo, bar, fizz))
}

object Main extends App {
  println(
    ChiselStage.emitSystemVerilog(
      gen = new Foo,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  )
}

What is the current behavior?

This generates:

// Generated by CIRCT firtool-1.62.0
module Foo(
  input        clock,
               reset,
               a,
               b,
               c,
  input  [7:0] foo,
               bar,
               fizz,
  output [7:0] out
);

  assign out = a ? foo : bar;
endmodule

What is the expected behavior?

This should either error, or function correctly because technically the last select bit is just dropped anyway. But it definitely shouldn't just incorrectly drop fizz.

Please tell us about your environment:

Other Information

What is the use case for changing the behavior?

chipsalliance / chisel

PriorityMux drops arguments if input sequences are not the same size #4444