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chipsalliance / chisel

Chisel: A Modern Hardware Design Language
https://www.chisel-lang.org/
Apache License 2.0
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Zero-Width Wire Support #847

Closed jackkoenig closed 1 year ago

jackkoenig commented 6 years ago

Type of issue: feature request

Related issues: https://github.com/freechipsproject/firrtl/issues/508 https://github.com/freechipsproject/firrtl/pull/530

Impact: API addition (no impact on existing code)*

IMO it should only be an addition; however, currently 0.U is the same as 0.U(1.W), and it would be a fairly substantial API change that could lead to subtle bugs if we changed it to 0.U(0.W). I'm of the opinion that we should not change that, rather zero-width wires could be created explicitly with 0.U(0.W) and via utilities that currently error out like log2Ceil and log2Floor.

Development Phase: request

What is the current behavior?

Zero-width wires don't really work

What is the expected behavior?

Zero-width wires should actually work

jackkoenig commented 1 year ago

This has been substantially implemented in Chisel and MFC.