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chipsalliance / dromajo

RISC-V RV64GC emulator designed for RTL co-simulation
Apache License 2.0
210 stars 63 forks source link

Update interrupt cosim support + generalize CLINT read/write #11

Closed ss2783 closed 4 years ago

ss2783 commented 4 years ago

This commit updates the cosim support for interrupts by checking for a pending dut interrupt alongwith the MIP/MIE checks. Some microarchitectures can delay the handling of interrupts and without the proposed changes the cosim will diverge.

This commit also generalizes the CLINT read/write to allow byte or half-word or word accesses (e.g. MSIP accesses)

et-tommythorn commented 4 years ago

It seems fine with the caveat that I don't currently have a way to test this. I may have to return to this in future, but I'll take it (thanks).