chipsalliance / dromajo

RISC-V RV64GC emulator designed for RTL co-simulation
Apache License 2.0
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Rewamp device model #16

Open et-tommythorn opened 4 years ago

et-tommythorn commented 4 years ago

This is forked off @ss2783's pull request #15 where extending the CLINT to handle sub-word accesses ran into trouble.

The fundamental problem is that the device model is currently called upon the load/stores directly and it's up to the handler to deal sub-word handling.

I think there's a model that works better:

  1. Allocate backing store (RAM) to the address space taken by the device
  2. All loads and stores just read the backing store as normal memory
  3. There's an optional pre-read hook which is called with hints about the access address and size. Devices without read side-effects don't need to provide this hook.
  4. There's an optional post-write hook which is called with hints about the access address and size. Devices without write side-effects don't need to provide this hook.
  5. There's an optional timer callback that can be registered to be called for every N ticks. Alternatively, it can schedule itself on a as-needed basis, TBD.

This significantly reduces the amount of code that needs to be written to support most devices and removes the sub-word access handling from devices (unless they really want to handle this in a special way).

et-tommythorn commented 4 years ago

On 2nd thought, the write-hook needs to be called pre-write as well (to handle R/O fields), but we can still simplify how the common write case happens.

That said, changing the PCI/virtio devices looks involved and I think we can make this change incrementally, as needed.

et-tommythorn commented 2 years ago

Looking at the PLIC this may not be practical; the PLIC covers a large address space, but is very sparsely populated.