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chipsalliance / dromajo

RISC-V RV64GC emulator designed for RTL co-simulation
Apache License 2.0
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[Bug Report] Page Fault should be thrown when Svnapot is not supported #57

Closed Phantom1003 closed 2 years ago

Phantom1003 commented 2 years ago

The specification (Volume II: RISC-V Privileged Architectures V20211203 Page 85) said: If Svnapot is not implemented, bit 63 remains reserved and must be zeroed by software for forward compatibility, or else a page fault exception is raised. Dromajo trace:

0 3 0x000000008000028c (0x0105051b) x10 0x0000000040201010
0 3 0x0000000080000290 (0x02a00593) x11 0x000000000000002a
0 3 0x0000000080000294 (0x00b52023)
0 3 0x0000000080000298 (0x000205b7) x11 0x0000000000020000
0 3 0x000000008000029c (0x3005b073)

Rocket/spike trace:

core   0: 0x000000008000028c (0x0105051b) addiw   a0, a0, 16
core   0: 0x0000000080000290 (0x02a00593) li      a1, 42
core   0: 0x0000000080000294 (0x00b52023) sw      a1, 0(a0)
core   0: exception trap_store_page_fault, epc 0x0000000080000294
core   0:           tval 0x0000000040201010
core   0: 0x0000000080000004 (0x34202f73) csrr    t5, mcause
core   0: 0x0000000080000008 (0x00800f93) li      t6, 8

Dromajo ignores the PTE N bit and calculates the address as a normal PTE.

Phantom1003 commented 2 years ago

Testcase is from here: https://github.com/riscv-software-src/riscv-tests/blob/master/isa/rv64ssvnapot/napot.S

napot.zip

et-tommythorn commented 2 years ago

Hi Phantom1003, thanks for your issue. We had a bit of internal discussion and we agree that Dromajo should be taken forward to ratified v1.12 of the privileged spec (which is AFAICT the same as the V20211203 you cite).

If you have a patch for this, we'd be happy to merge it. Otherwise it will get these eventually, but it will take a bit.