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chipsalliance / dromajo

RISC-V RV64GC emulator designed for RTL co-simulation
Apache License 2.0
210 stars 63 forks source link

Summary: creating single boot ROM for multicore configs #80

Open kabylkas opened 1 year ago

kabylkas commented 1 year ago

The motive for this PR is explained in #79.

This pull request introduces the implementation for the enhancement. When the checkpoint is saved, a single boot ROM is generated for N cores. The boot code is divided into N sections, where N represents the number of cores. Each core will generate its own recovery code and write it to its designated section. In addition to the recovery code, each core initializes with a preamble code that reads the hart_id and calculates the program counter (PC) based on the id.

Please let me know what you think.

et-tommythorn commented 5 months ago

Sorry, it seems I missed a bunch of github notifications. Let me look at this.