SYMBIFLOW-CLASSROOM Surelog/UHDM doesn't handle typed parameters

[nelsobe]

The following code throws a compile error on the parameter statement when compiled with the UHDM. Removing the 'integer' solves it. It compiles and runs correctly with both Vivado as well as the original Yosys front end.

module top(
    input logic[3:0] sw,
    output logic [3:0] led
);

parameter integer OFFSET=5;

assign led = sw + OFFSET;

endmodule

A complete test case is below. The command line used to compile with the latest version of f4pga-examples is:

SURELOG_CMD="-parse -DSYNTHESIS" make

Note that my Makefile sets the part itself and so that is not included.

Issue288.zip

[rkapuscik]

Thanks for reporting this. Integer support was added to plugin in https://github.com/chipsalliance/yosys-f4pga-plugins/pull/290. I will let you know when the fix will be available through conda.

[jcrob2]

Using the following timestamp and hash, the issue still exists. Timestamp: 20220606-234655 Hash: 1667c14

I've included a file that contains a list of the content/versions of the conda environment that we have. conda_list.txt

[rkapuscik]

This should be already fixed, please update the plugin to the newest version as described here to verify.

[Zach227]

@nelsobe I have retested this bug with the latest install and have verified that it is fixed. This issue can be closed.

[nelsobe]

@Zach227 Thanks, closing it now...