Unable to handle Shift with Ternary operator

[westonMS]

Shift-Ternary Bug

Using Surelog plugin, with Yosys, Yosys gives the following bug
ERROR: Unsupported expression in mark_as_unsigned!

Yosys parser is able to compile the program without using Surelog

The error is caused by a shift operator followed by a ternary operator. Shifting either directions causes the bug. So does the <<< or >>> shift operator. Problem Statement : (0)<<(0)?(0):(0);

Simplified code that causes error:

module top();
logic x;
assign x = (0)<<((0)?(0):(0));
endmodule

Source code generated using Verismith

[westonMS]

If the Ternary operation is not in parenthesis, the bug will not occur

[rkapuscik]

Thanks for reporting, we will investigate this.

[rkapuscik]

This should be already fixed, please update the plugin to the newest version as described here to verify.

[Zach227]

I have re-tested this with the latest plugin and the design works now. However, we want fixes to be available to all users when they use the main install. I re-installed the tool-chain with the latest install instructions and this is not fixed without manually updating the plugin.

[umarcor]

@Zach227 the environment for xc7 was updated very few hours ago: https://github.com/chipsalliance/f4pga-examples/commits/main. Did you fetch and pull the latest changes from the main branch 2h ago (when you wrote the comment)?

[Zach227]

I retested this with the latest update and the issue is now resolved.