Questions regarding the purpose and function of v2x

[MidsummerNight]

So I've been trying to get an overall understanding of the Symbiflow project with a particular interest in how to automatically generate XML-format architecture description files that can be fed into the VTR stage, which was why I came across v2x. However after a month of researching I still feel frustrated so I sent @mithro an email with a long list of questions I gathered, and he in turn suggested that I take these to a public space so the discussions can be read by and thus help everyone. Now I'm complete new to the FPGA field and I don't have an EE background so pardon me for asking seemingly dumb questions -- I've gleaned through all the documentations and your presentation videos yet still couldn't get my head straight.

Say I'm designing an experimental FPGA myself and want to see if the Symbiflow toolchain can correctly implement an user design (let's say a small CPU) on this experimental FPGA. Suppose I have the full RTL code of my FPGA and the CPU, both written in Verilog. The VTR stage needs to read an XML file describing my FPGA's architecture, which I could either write by hand (a tedious job -- "writing xml sucks" as @kgugala put it in his talk, or according to v2x's description, generate the XML files with v2x. However my exprience was:

1. Large, complicated Verilog files can't seem to be correctly converted. In my case, sometimes Yosys wouldn't even accept the Verilog file, reporting unexpected '[', expecting TOKEN_ID or ',' or '=' or ')' when it reads wire variables like wire [63:0] BL and BL[0], BL[1] etc.
2. Naturally I tried to feed v2x smaller, single-module Verilog files containing wide wires like wire [63:0] BL and BL[0] adn found out Yosys accepted them just fine and these small test files were successfully converted in model and pb_type XMLs.
3. Though in some cases Yosys had trouble determining what the top module is when proccessing those small files, which is quite odd. Changing the file name into ***.sim.v and changing the module name into TOP would sometimes work. Sorry I didn't save the test files nor the terminal outputs so I couldn't provide further details.
4. Tests examples in the /python-symbiflow-v2x/tests/ directory can be converted in XML files without problems.

After runnning into the issues above and reading the documentations again I now have these questions:

1. All tests in the /python-symbiflow-v2x/tests/ directory are single-module circuits, and since Yosys has trouble translating my large, complicated Verilog files into json files despite the Verilog files not having syntax errors, does this mean v2x or Yosys's write_json command can only handle single-module circuits? Which would be strange if true as I haven't seen people bringing this up at Yosys's Github.
2. @mithro gave me a brief explanation in his email stating that v2x converts the "building blocks" (written in Verilog) of an FPGA into an XML file readable by VPR. Does this confirm v2x is for converting single-module Verilog descriptions only?
3. The flow diagram shows a mux_gen.py generating xxx.sim.v files which are fed into v2x and even directly generating xxx.model.xml, xxx.pb_type.xml files itself. What is this mux_gen.py and its purpose? Why have I never seen it in action in v2x, arch-def and prjxray?
4. How are the model and pb_type XML files pieced together into the final big architecture XML file that's used by VPR? I can't find the tools to do so in Symbiflow.

Sorry for asking 4 questions in a single issue, I'm doing so since this is more of a general discussion than reporting a specific detail. @kgugala @acomodi Since you two seem to be the main devs of v2x I'll be more than happy if you can help me walk through my tough early steps, thanks!