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chipsalliance / f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
https://f4pga-v2x.readthedocs.io/en/latest/
Apache License 2.0
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Why v2x don't support routing mux which has output bus? #114

Closed KKtiandao closed 2 years ago

KKtiandao commented 2 years ago

I view the code of function make_container_pb. The 'sinks' of routing mux is an array struct. But there are some 'assert' to judge if routing mux has multi ouputs. So in the case of mux with bus in and output, the 'assert ' will be false. 企业微信截图_16507844717957 https://github.com/chipsalliance/f4pga-v2x/blob/11bc48d06352250bb878d42eedefdc6bbaa6e402/v2x/vlog_to_pbtype.py#L672 I commented the asserts and made sucess in arch_def flow. But I don't know if these comments will result any other bugs. Hope helps.

kgugala commented 2 years ago

According to the VPR docs (https://docs.verilogtorouting.org/en/latest/arch/reference/#tag-%3Cmuxname=) buses are not supported. There is a note saying:

Buses are not yet supported so all muxes must use one bit wide data only!

The assert in v2x is to guard exactly this. If this is not true anymore we should update VPR docs (and v2x to support this)

KKtiandao commented 2 years ago

@kgugala Thanks. I have another questions. Can v2x generate the pb_type subtag on timing like ?

mithro commented 2 years ago

See https://python-symbiflow-v2x.readthedocs.io/en/latest/examples/vtr/dff/README.html

KKtiandao commented 2 years ago

@mithro Thanks!