search

chipsalliance / f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
https://f4pga-v2x.readthedocs.io/en/latest/
Apache License 2.0
10 stars 12 forks source link

Yosys: do not optimize designs during evaluation #20

Closed kgugala closed 4 years ago

kgugala commented 5 years ago

This PR add a possibility to disable Yosys optimization during design evaluation. This is required to correctly handle output buffers models. Those models have inputs, but no outputs. Yosys removes such cells during optimization.

mithro commented 5 years ago

I think this is needed. But you should also add a pass which adds (* keep *) to the modules which have the properties.

mithro commented 4 years ago

@kgugala Is this still needed?

mithro commented 4 years ago

I think this is no-longer needed?