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chipsalliance / f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
https://f4pga-v2x.readthedocs.io/en/latest/
Apache License 2.0
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Fixes for interconnect generation #28

Closed mkurc-ant closed 4 years ago

mkurc-ant commented 4 years ago

This PR fixes two important bugs in interconnect generation:

  1. Generation of connections between ports of the same pb_type

    V2X was completely missing generating interconnects for such cases. With this PR they are handled correctly

  2. Handling a "pass-through" mode of a pb_type

    When defining a cell with a mode that does not have any children, the interconnect was generated incorrectly. This PR introduces a detection of such situations so no "empty" pb_type for the mode is generated. Istead, an iterconnect is generated that binds the passthrough connection ports.