Support for clock buffer/mux modeling

[mkurc-ant]

This PR adds a feature that allows to model clock buffers and multiplexers in V2X.

• Added new attribute COMB_INCLUDE_CLOCKS. When specified on a clock input port allows it to have combinational relations with other ports.
• Added a new attribute NO_SEQ. When set to 1 on an input port prevents V2X from attaching clock list to it.

[mithro]

@mkurc-ant -- Recently when looking at the SDC parsing stuff I came across a document from Xilinx which describes how various values can be set using verilog attributes / properties. These seem a lot like the type of things we need in v2x, so I copied them to the spreadsheet https://docs.google.com/spreadsheets/d/1G-E2Dq8YG4g9Z6mTygpumwlI_vNlFUQinc9gMgePfec/edit#gid=1349094793

Could you take a look over these values and see if any of these match enough that we should be using them instead?

[mkurc-ant]

@mithro I've gone through them. In my opinion for now only the (* clock_signal = "{yes|no}" *) matches the CLOCK attribute currently implemented in V2X.

We basically need most of the attributes to control XML generation an it is loosely coupled with actual synthesis/implementation control.

[mkurc-ant]

Requires https://github.com/SymbiFlow/python-symbiflow-v2x/pull/76 for the CI to pass.

[mithro]

@mkurc-ant - I think we can probably merge this after the docs update?

[mkurc-ant]

@mithro Yes. Once docs update is merged I'll add docs to this one.

[mkurc-ant]

@mithro I've rebased and updated docs.

[mkurc-ant]

@mithro I've incorporated your requested changes. Could you re-review?

[mkurc-ant]

@mithro Do you have any other questions to this PR or can we merge it?

[mithro]

Please update the pull request comment and then feel free to merge.

[mithro]

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