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chipsalliance / f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
https://f4pga-v2x.readthedocs.io/en/latest/
Apache License 2.0
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muxes: add name of routing mux as metadata prefix #84

Closed acomodi closed 3 years ago

acomodi commented 3 years ago

Signed-off-by: Alessandro Comodi acomodi@antmicro.com

Without this change, the information on which routing mux has a specific input selected is lost.

Output before:

<mux input="COMMON_SLICE.AX COMMON_SLICE.A5LUT_O5 COMMON_SLICE.A6LUT_O6" name="AFFMUX1" output="SLICE_FF.D[15]">
    <metadata>
        <meta name="fasm_mux">
            COMMON_SLICE.AX : BYP
            COMMON_SLICE.A5LUT_O5 : D5
            COMMON_SLICE.A6LUT_O6 : D6
        </meta>
        <meta name="type">bel</meta>
        <meta name="subtype">routing</meta>
    </metadata>
</mux>

Output after:

<mux input="COMMON_SLICE.AX COMMON_SLICE.A5LUT_O5 COMMON_SLICE.A6LUT_O6" name="AFFMUX1" output="SLICE_FF.D[15]">
    <metadata>
        <meta name="fasm_mux">
            COMMON_SLICE.AX : AFFMUX1.BYP
            COMMON_SLICE.A5LUT_O5 : AFFMUX1.D5
            COMMON_SLICE.A6LUT_O6 : AFFMUX1.D6
        </meta>
        <meta name="type">bel</meta>
        <meta name="subtype">routing</meta>
    </metadata>
</mux>